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XC2S50E-6TQ144C Field Programmable Gate Array FPGA IC 102 32768 1728 144-LQFP

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XC2S50E-6TQ144C Field Programmable Gate Array FPGA IC 102 32768 1728 144-LQFP

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Brand Name :Original
Model Number :XC2S50E-6TQ144C
Certification :Original
Place of Origin :Original
MOQ :1
Price :Negotiation
Payment Terms :TT
Supply Ability :100
Delivery Time :3-4days
Packaging Details :carton box
Package :Tray
Number of LABs/CLBs :384
Number of Logic Elements/Cells :1728
Total RAM Bits :32768
Number of I/O :102
Number of Gates :50000
Voltage - Supply :1.71V ~ 1.89V
Operating Temperature :0°C ~ 85°C (TJ)
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XC2S50E-6TQ144C Field Programmable Gate Array (FPGA) IC 102 32768 1728 144-LQFP

XC2S50E-6TQ144C are from factory inventory, pls check your demands and pls contact us with with target price.

Specifications of XC2S50E-6TQ144C

Type Description
Category Integrated Circuits (ICs)
Embedded
FPGAs (Field Programmable Gate Array)
Mfr AMD
Series Spartan®-IIE
Package Tray
Number of LABs/CLBs 384
Number of Logic Elements/Cells 1728
Total RAM Bits 32768
Number of I/O 102
Number of Gates 50000
Voltage - Supply 1.71V ~ 1.89V
Mounting Type Surface Mount
Operating Temperature 0°C ~ 85°C (TJ)
Package / Case 144-LQFP
Supplier Device Package 144-TQFP (20x20)
Base Product Number XC2S50E


Features of XC2S50E-6TQ144C

Second generation ASIC replacement technology

- Densities as high as 15,552 logic cells with up to 600,000 system gates

- Streamlined features based on Virtex®

- E FPGA architecture-Unlimited in-system reprogrammability

- Very low cost-Cost-effective 0.15 micron technology

System level features

- SelectRAM™ hierarchical memory:

· 16 bits/LUT distributed RAM

· Configurable 4K-bit true dual-port block RAM

· Fast interfaces to external RAM

- Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant

- Low-power segmented routing architecture

- Dedicated carry logic for high-speed arithmetic

- Efficient multiplier support

- Cascade chain for wide

- input functions

- Abundant registers/latches with enable, set, reset

- Four dedicated DLLs for advanced clock control

· Eliminate clock distribution delay

· Multiply, divide, or phase shift-Four primarylow

- skewglobalclockdistributionnets

- IEEE 1149.1 compatible boundary scan logic

Versatile I/O and packaging

- Pb-free package options

- Low

- cost packages available in all densities

- Family footprint compatibility in common packages

- 19 high-performance interface standards·LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL·LVDS and LVPECL differential I/O

- Up to 205 differential I/O pairs that can be input, output, or bidirectional

- Hot swap I/O (CompactPCI friendly)

Core logic powered at 1.8V and I/Os powered at 1.5V, 2.5V, or 3.3V

Fully supported by powerful Xilinx® ISE® development system

- Fully automatic mapping, placement, and routing

- Integrated with design entry and verification tools

- Extensive IP library including DSP functions and soft processors

Spartan-IIE Family Compared to Spartan-II Family

Higher density and more I/O

Higher performance

Unique pinouts in cost-effective packages

Differential signaling-LVDS, Bus LVDS, LVPECL

• VCCINT = 1.8V-Lower power-5V tolerance with external resistor-3V tolerance directly

PCI, LVTTL, and LVCMOS2 input buffers powered by VCCO instead of VCCINT

Unique larger bitstream


Environmental & Export Classifications of XC2S50E-6TQ144C

Attribute Description
RoHS Status RoHS non-compliant
Moisture Sensitivity Level (MSL) 3 (168 Hours)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8542.39.0001


XC2S50E-6TQ144C Field Programmable Gate Array FPGA IC 102 32768 1728 144-LQFP

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